Single-Bit Segment Encoding
A new OS-level encoding architecture that conveys n bits of data through a single bit-set operation — reducing switching activity, energy consumption, and heat output across every layer of the compute stack.
The physics of bit transitions
Every time a bit changes state — from 0 to 1 or 1 to 0 — it consumes energy and generates heat. In a conventional n-bit register, storing or changing a value can require up to n individual bit transitions. Across billions of operations per second in a modern data center, that switching activity is a primary driver of power draw and thermal load.
Dash Computing's encoding architecture changes at most one bit per value update, regardless of how many bits the value represents. Changing a value from one n-bit number to another requires clearing at most one bit position and setting at most one bit position — two transitions maximum, always, for any value of n.
Inspired by PSK modulation
Inspired by phase-shift keying
Modems solve a similar problem in data communications using PSK modulation: a carrier signal occupies one of 2ⁿ discrete phase states, so each transmitted symbol conveys n bits. Dash Computing applies the same principle inside the computing system itself — each 2ⁿ-bit segment acts as a symbol with 2ⁿ distinguishable states, and the OS selects one state by setting one bit.
4 phase states → 2 bits/symbol (PSK) ↔ 32-bit segment → 5 bits/set-bit (Dash)
Encoding architecture
How the encoding works
Each n-bit value is represented not by n bits set to 0 or 1, but by the position of a single set bit within a 2ⁿ-bit segment.
FIG. 4 — Worked example from the patent
A 15-bit payload (100110000011111) is divided into three 5-bit values: 10011 (19), 00000 (0), and 11111 (31). Each is encoded into a 32-bit segment by setting exactly one bit at the position equal to the value.
15-bit payload: 1 0 0 1 1 | 0 0 0 0 0 | 1 1 1 1 1
5-bit value: 19 (10011)
5-bit value: 0 (00000)
5-bit value: 31 (11111)
Interactive: compare bit transitions
Conventional 5-bit encoding
From
To
Dash Computing encoding (32-bit segment)
OS-level implementation
Six software modules
Partitioning Module
Divides processor registers, primary memory pages, and secondary storage blocks into segments of 2ⁿ bit positions. For n=5, a 64-bit register holds two 32-bit segments; a 256-bit vector register holds eight independent lanes. A 4 KB memory page holds 1,024 segments.
Payload Module
Receives payload data from write calls, device driver buffers, or memory transfers. Divides the bit sequence into consecutive n-bit values, padding the final value if needed and recording the original payload length for lossless reconstruction.
Encoding Module
Encodes each n-bit value into its segment by shifting a binary 1 left by the value — a single shift-left instruction. Alternatively uses a 2ⁿ-entry lookup table or a hardware decoder circuit. One store instruction writes the encoded segment.
Occupancy Enforcement Module
Enforces the single-bit occupancy rule using a population-count instruction. Verifies each segment has exactly one set bit before the write proceeds. Detects corruption by flagging segments with population count > 1 during reads.
Decoding Module
Recovers the n-bit value from a segment using a count-trailing-zeros instruction (TZCNT on x86, RBIT+CLZ on ARM). Reconstructs the full payload by concatenating decoded values in segment order and truncating to the recorded original length.
File System Module
Formats secondary storage with a new file system type (analogous to ext4 or NTFS) that divides each storage block into 2ⁿ-bit segments and records n in the superblock metadata. A 4 KB block with n=5 stores 640 bytes of payload across 1,024 segments.
Full-stack coverage
Every layer of the compute stack
The same encoding parameter n is applied uniformly across CPU registers, GPU memory, DRAM, and secondary storage. A segment encoded on disk loads into RAM and into a CPU register without re-encoding — the set bit position is identical at every layer.
CPU Registers
A 64-bit general-purpose register holds two 32-bit segments. A 256-bit vector register holds eight independent 32-bit lanes — one vector store writes eight encoded segments conveying 40 bits of payload.
GPU Memory
The GPU driver partitions graphics memory (GDDR / HBM) into 32-bit segments. Each thread in a 32-thread warp holds one segment; a single store across the warp writes 32 segments conveying 160 bits. Encoding uses shift-left; decoding uses find-first-set or count-leading-zeros.
Primary Memory (DRAM)
The OS memory manager reserves physical pages and marks them as segmented. A 4 KB page holds 1,024 segments of 32 bits. Segmented pages are mapped read-only to user processes; writes route through the encoding and occupancy enforcement modules via page-fault handler.
Secondary Storage
The file system module formats drives with a new volume type. The superblock records n, block size, and allocation metadata. A 4 KB block with n=5 stores 640 bytes of payload. Segments encoded on disk are loaded into RAM and CPU registers in the same encoded form — no re-encoding at each layer.
Technical differentiators
Why it's different
At most 2 transitions per value change
Conventional n-bit encoding can require up to n bit transitions for a single value change. Dash Computing's encoding always requires at most 2 — clear the old bit, set the new one — regardless of n.
Unified across the full stack
The same value of n is applied to CPU registers, DRAM, GPU memory, and disk. A segment encoded on storage loads into RAM and into a register without re-encoding. The set bit position is identical at every layer.
Native instruction compatibility
Encoding uses shift-left (SHL). Decoding uses count-trailing-zeros (TZCNT / CLZ). Equality comparison works directly on encoded segments without decoding. All operations map to single native CPU and GPU instructions.
OS-level, application-transparent
The encoding layer operates as a kernel module, memory manager subsystem, device driver, or file system driver. Applications issue standard read/write system calls. The OS handles encoding and decoding transparently.
Ready to explore integration?
Talk to our engineering team about deploying the encoding layer in your infrastructure.